1. Field of the Invention
The present invention relates to electronic systems containing synchronous dynamic random access memory. More particularly, this invention relates to a method and apparatus for improving bus usage between memory components and other devices thus allowing for increased line of communication or transfer of data, commands, status, or any other electronic messages during previously unusable clock cycle periods.
2. The Background Art
In computer systems, calculators, televisions, electronic instruments, and other electronic devices, it is usually critical that system resources be used as efficiently as possible so that maximum efficiency may be obtained.
In systems utilizing Synchronous Dynamic Random Access Memory (SDRAM) for data storage, burst transfer modes are often utilized which allow SDRAM components to initiate access to and transfer of single or multiple blocks of data with a single command. Once a burst command is issued by the memory controller, the data is transferred over data lines between the memory controller and SDRAM as one continuous stream. It will be evident that, although the use of SDRAM components may improve system performance, further gains may be obtained through the use of the present invention.
FIG. 1 is a block diagram depicting a typical prior art interface between a memory controller and SDRAM components.
Referring to FIG. 1, memory controller 10 receives instructions from other system components over lines 12. These other system components may be graphics controllers, audio controllers, or any other system component requiring the use of SDRAM components for storage of data. These other system components may or may not be embedded within the same ASIC or part of the same system as the memory controller. In general, the term memory controller refers to circuitry which interfaces with memory, which, in this case, is SDRAM.
After receiving instructions to store or retrieve data, memory controller 10 communicates with SDRAM memory 14 using many different lines: Row Address Strobe (RAS) 16, Column Address Strobe (CAS) 18, Address lines 20, Data lines 22, write enable lines 24, and chip select lines 26. Memory 14 comprises one or more SDRAM memory components arranged so as to be addressed as an array of memory cells.
A periodic pulse is supplied to the system on Clock (CLK) line 28 which is necessary for synchronization between the various components of the system. This periodic pulse may be supplied by the memory controller or any other suitable source as is well known in the art.
Once memory controller 10 has issued a valid data transfer command to SDRAM memory 14, data begins to flow into or out of SDRAM memory 14 using data lines 22 through memory controller. The source or destination of this data may either be inside or outside of the system.
Where necessary, the memory controller may terminate any transfer already in progress. After the last byte of the requested block of data has been transmitted, another command to read or write additional blocks of data may be issued.
While this method of utilizing SDRAM components may be suitable for its intended purposes, RAS 16, CAS 18, address lines 20, and write enable lines 24 remain idle during the data transfer between SDRAM memory 14 and memory controller 10, typically between two and ten clock cycles. If these lines were able to be utilized for other purposes such as to transfer blocks of data between other system components, system performance would increase by making more efficient use of system resources. It would therefore be beneficial to provide an apparatus and method for managing the use of these idle lines while burst data transfers are taking place.